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International conference A Monolithically integrated 1-MHz 400-V GaN half-bridge power converter with dual-stage gate drivers in a 650-V GaN-on-SOI process ; by Hayeon Kim, Yewon Choi, Donghun Kim, and Jongsun Kim ; 2024 International Conference on Electronics, Information, and Communication (ICEIC), Taipei, Taiwan, Jan. 28-31, pp. , 2024 A GaN driver IC with a TDC-based dead-time controller for GaN DC-DC Buck converters ; by Yongseung Lee, Donghun Kim, and Jongsun Kim ; 2023 International SoC Design Conference (ISOCC), Jeju, Oct. 25-28, pp. 33-34, 2023
An integrated GaN gate driver with a reverse conduction controller ; by Donghun Kim, Yongseung Lee, Gyoul Han, and Jongsun Kim ; 2023 International Conference on Electronics, Information, and Communication (ICEIC), Bangkok, Singapore, Feb. 5-8, pp. 743-744, 2023
A fast lock all-digital programmable N/M-ratio MDLL frequency multiplier using a variable resolution TDC ; by Chaeyoung Jang, Pil-ho Lee*, Sang-Jae Rhee*, Ki-Hwan Choi*, and Jongsun Kim (* Samsung Electronics) ; 2022 International Conference on Electronics, Information, and Communication (ICEIC), Jeju, Korea, Feb. 6-9, pp. 601-602, 2022
A 7.68 GHz fast-lock low-jitter digital MDLL ; by Junghoon Jin, Seungjun Kim, Sunguk Choi, Pil-ho Lee*, Sang-jae Rhee*, Ki-hwan Choi*, and Jongsun Kim (* Samsung Electronics) ; 2021 International SoC Design Conference (ISOCC), Jeju, Ramada Plaza, Oct. 6-9, pp. 311-312, 2021
; DOI: 10.1109/ISOCC53507.2021.9613940
A 0.8-3.5 GHz shared TDC-based fast-lock all-digital DLL with a built-in DCC ; by Taeyeon Kim and Jongsun Kim ; 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, May 22-28, 2021, pp. 1-4; DOI:<!---->10.1109/ISCAS51556.2021.9401335
An all-digital MDLL for programmable N/M-ratio frequency multiplication ; by Taeyeon Kim, Sunguk Choi, and Jongsun Kim (우수논문상 DBHiTek Award 수상) ; 2020 International SoC Design Conference (ISOCC), Yeosu, pp. 230-231, Oct. 21-24, 2020 ; DOI: 10.1109/ISOCC50952.2020.9332935
A 30 Gb/s all-digital CDR with a phase error compensator ; by Kunhoo Park, Heejae Hwang, and Jongsun Kim ; 2020 International Conference on Electronics, Information, and Communication (ICEIC), Barcelona, Spain, Jan. 19-22, 2020 ; DOI: 10.1109/ICEIC49074.2020.9051017 A low-power 20 Gbps multi-phase MDLL-based digital CDR with receiver equalization ; by Heejae Hwang and Jongsun Kim ; 2019 International SoC Design Conference (ISOCC), Jeju, Oct. 6-9, 2019 ; DOI: 10.1109/ISOCC47750.2019.9078536 A fast-locking all-digital MDLL frequency multiplier ; Changjun Lee and Jongsun Kim ; 2019 AWAD, Busan, July 1-3, 2019 An all-digital frequency synthesizer for fractional-ratio on-chip clock generation ; Taeyeon Kim and Jongsun Kim ; 2019 MicDAT, Amsterdam, The Netherlands, May 2019 A 7-GHz fast-lock 2-step TDC-based all-digital DLL for post-DDR4 SDRAMs ; by Dongjun Park and Jongsun Kim ; 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 2018 ; DOI: 10.1109/ISCAS.2018.8351396 A fast-locking all-digital multiplying DLL for fractional-ratio dynamic frequency scaling ; by Jongsun Kim ; 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 2018 (IEEE CAS Transactions Papers) A low-jitter digital DLL for high-speed memory interface ; by Junsub Yoon and Jongsun Kim ; 2018 ITC-CSCC, Bangkok, Thailand, July 4-7, 2018 A low-power SerDes transceiver for high-speed memory interface ; by Kunhoo Park and Jongsun Kim ; 2018 AWAD, Kitakyushu, Japan, July 2-4, 2018 A 16-Gbps low-power transceiver for high-speed serial links ; by Jongsun Kim and Jahyun Gu ; 2018 MicDAT, Barcelona, Spain, June 20-22, 2018 A programmable clock frequency multiplier for low-power SoC ; by Jongsun Kim and B. Bae ; 2018 International Conference on Electronics, Information, and Communication (ICEIC), Honolulu, Hawaii, Jan. 24-27, 2018 A low-power SerDes for high-speed on-chip networks ; by Dongjun Park, Junsub Yoon, and Jongsun Kim (ISOCC Best Paper Award 수상) ; 2017 International SoC Design Conference (ISOCC), Nov. 2017 ; DOI: 10.1109/ISOCC.2017.8368879 A 0.15 to 2.2 GHz all-digital delay-locked loop ; by Dongjun Park, G. Park, and Jongsun Kim ; 2017 IEEE International NEWCAS Conference (NEWCAS), Strasbourg, France, June, 2017 : DOI: 10.1109/NEWCAS.2017.8010155 A low-power multiplying DLL-based fractional-N frequency synthesizer ; by Junsub Yoon and Jongsun Kim ; 2017 AWAD, Gyeongju, July 3-5, 2017 A MDLL-based Multi-Phase Clock Multiplier ; by Junsub Yoon and Jongsun Kim ; 2016 International SoC Design Conference (ISOCC), Oct. 2016 ; DOI: 10.1109/ISOCC.2016.7799770<!-- end ngIf: ::record.doi --> A Fast-Locking Clock Multiplying DLL ; by Jongsun Kim and B. Bae ; 2016 International SoC Design Conference (ISOCC), Oct. 2016 ; DOI: 10.1109/ISOCC.2016.7799773 A Digital Delay-Locked Loop for High-Speed DRAMs ; by junsub Yun and Jongsun Kim ; 2016 AWAD, Hakodate, Japan, July 4-6, 2016 A 10 Gbps SerDes for wireless chip-to-chip communication ; by S. Han, Taegyu Kim, Jintae Kim, and Jongsun Kim ; International SoC Design Conference (ISOCC) 2015, pp. , Nov. 2015 (ISOCC Best Paper Award 수상) ; DOI: 10.1109/ISOCC.2015.7401630 A Single Chip Li-Ion Battery Protection IC with Low Standby Mode Auto Release ; by Seunghyeong Lee, Yongjae Jeong, Yungwi Song, and Jongsun Kim ; ISOCC 2014, pp. 38-39, Nov. 2014 (Silicon Mitus Award 수상) ; DOI: 10.1109/ISOCC.2014.7087583 Design of a wide dynamic range RMS power detector ; by D. Lee and Jongsun Kim ; 2014 AWAD, July, 2014 Design of a fractional-ratio multiplying delay locked loop ; by S. Han, B. Bae, and Jongsun Kim ; 2014 AWAD, July, 2014 A 0.1-1.5 GHz All-Digital Phase Inversion Delay-Locked Loop ; by S. Han and Jongsun Kim ; 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) Nov. 2013 ; DOI: 10.1109/ASSCC.2013.6691052 An 8.0 Gb/s Low-Swing Low-Power Transceiver for Mobile Interface ; by Jahyun Ku, SW Han and Jongsun Kim ; 2013 AWAD (Asia-Pacific Workshop on Fundamentals and Applications of. Advanced Semiconductor Devices), June, 2013 A High-Resolution Wide-Range Dual-Loop Digital Delay-Locked Loop Using a Hybrid Search Algorithm ; by S Han and Jongsun Kim ; 2012 IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2012 ; DOI: 10.1109/IPEC.2012.6522683 A Programmable Delay Locked Loop Based Clock Multiplier ; by S. Lee, Geontae Park, Hyungtak Kim and Jongsun Kim ; 2012 International SoC Design Conference (ISOCC), Nov. 2012 ; DOI: 10.1109/ISOCC.2012.6407056 A Wide Range and High Resolution CMOS DCC ; by S Han and Jongsun Kim ; 2012 AWAD (Asia-Pacific Workshop on Fundamentals and Applications of. Advanced Semiconductor Devices), June, 2012 Double Edge Trailing PWM Based Full Digital Audio Amplifier Design ; by Se-Weon Heo and Jongsun Kim ; IEEE ICCE (International Conference on Consumer Electronics), Jan., 2012 Wireline/Wireless RF-Interconnect for future SoC ; by Sai-Wang Tam, M. Fracnk Chang, Jongsun Kim, and G. Byun ; IEEE RFIT (International Symposium on Radio-Frequency Integration Technology), Dec., 2011 (Invited Paper) ; DOI: 10.1109/RFIT.2011.6141771
Wireline and Wireless RF-Interconnect for next generation SoC Systems
; by Sai-Wang Tam, M. Frank Chang, and Jongsun Kim ; IEEE MWSCAS (International Midwest Symposium on Circuits and Systems), Aug., 2011 (Invited Paper) ; DOI: 10.1109/MWSCAS.2011.6026279 A mixed-mode duty cycle corrector for low-power standby mode operation ; by S. Han and Jongsun Kim ; 2011 AWAD (Asia-Pacific Workshop on Fundamentals and Applications of. Advanced Semiconductor Devices), June, 2011 An 8.4Gb/s 2.5pJ/b Mobile Memory I/O Interface using Bi-directional and Simultaneous Dual (Base+RF)-Band Signaling ; by G. Byun, Yanghyo Kim, Jongsun Kim, Sai-Wang Tam, Jason Cong, Glenn Reinman, and M. Frank Chang ; IEEE 2011 International Solid-State Circuits Conference (ISSCC), pp. 2011 RF Interconnect Technology for On-chip and Off-chip Communication ; by Jongsun Kim, G. Byun, and M. Frank Chang ; 2010 AWAD (Asia-Pacific Workshop on Fundamentals and Applications of. Advanced Semiconductor Devices), IEICE ED2010-75, pp. 105-108, July, 2010 An RF/Baseband FDMA-Interconnect Transceiver for Reconfigurable Multiple Access Chip-to-Chip Communication ; by Jenwei Ko, Jongsun Kim, Zhiwei Xu, Qun Gu, Charles Chien and M. Frank Chang ; IEEE 2005 International Solid-State Circuits Conference (ISSCC), Feb, 2005, pp. 338-339 A Low Power Capacitive Coupled Bus Interface Based on Pulsed Signaling ; by Jongsun Kim, Jung-Hwan Choi, Chang-Hyun Kim, M. Frank Chang and Ingrid Verbauwhede ; IEEE 2004 Cicustom Integrated Circuits Conference (CICC), Oct, 2004, pp. 35-38 Three-Dimensional Circuit Integration Based on Self-Synchronized RF-Interconnect using Capacitive Coupling ; by Qun Gu, Zhiwei Xu, Jongsun Kim, Jenwei Ko, M. Frank Chang ; 2004 Symposium on VLSI Technology, Digest of Technical Papers, pp. 96-97, Jun. 2004, USA A 2-Gbps/pin Source Synchronous CDMA Bus Interface with Simultaneous Multi-Chip Access and Reconfigurable I/O Capability ; by Jongsun Kim, Zhiwei Xu, M. Frank Chang ; IEEE 2003 Cicustom Integrated Circuits Conference (CICC), Sept. 2003, pp. 317-320 Reconfigurable Memory Bus Systems using Multi-Gbps/pin CDMA I/O Transceivers ; by Jongsun Kim, Zhiwei Xu, M. Frank Chang ; IEEE Internationl Symposium on Circuits and Systems (ISCAS), Vol.2, pp. II-33-36, May, 2003. A 2.7 Gb/s CDMA-Interconnect Transceiver Chip Set with Multi-Level Signal Data Recovery for Re-configurable VLSI Systems ; by Zhiwei Xu, Hyunchol Shin, Jongsun Kim, M.F. Chang and Chales Chien ; IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers. pp. 82-83, Feb, 2003 An Area-Efficient 2GB/s 256Mb Packet-based DRAM with Daisy-Chained Redundancy Scheme ; by B-S. Moon, J-W. Chai, J-S. Kim, S-M. Yim, S-A. Kim, C. Kim and S.-I. Cho ; IEEE 2001 Symposium on VLSI circuits (SOVC), pp.35-36, 2001 Domestic conference TDC 기반 Registering Clock Driver용 완전 디지털 PLL
; 채창훈, 김종선 ; 2023 반도체공학회 하계학술대회, 경주, July. 17, 2023
GaN Power Switch 기반 30V-to-12V DC-DC Buck Converter IC
; 김동훈, 이용승, 김하연, 김종선 ; 2023 반도체공학회 하계학술대회, 경주, July. 17, 2023?
TDC를 활용해 빠른 Settling Time을 갖는 GaN Gate Driver IC
; 이용승, 김동훈, 김종선 ; 2023 반도체공학회 하계학술대회, 경주, July. 17, 2023?
PVT 변화 보상기능을 가지는 Time-to-Digital Converter
; 신은호, 김종선 ; 2023 반도체공학회 하계학술대회, 경주, July. 17, 2023 LDO를 활용한 PVT Insensitive Bandgap Reference
; 김하연, 최예원, 김종선 ; 2023 SoC 학술대회, 국민대학교 매래관, May. 13, 2023? GaN Power Switch 기반 Buck Converter IC 설계
; 김동훈, 이용승, 김하, 김종선 ; 2023 SoC 학술대회, 국민대학교 매래관, May. 13, 2023 고해상도 TDC를 이용한 고효율 GaN Gate Driver IC
; 이용승, 김동, 김종선 ; 2023 SoC 학술대회, 국민대학교 매래관, May. 13, 2023 역전도 제어기를 구비한 BCD기반 고효율 GaN Gate Driver IC
; 김동훈, 이용승, 한결, 김종선 2023 제23회 한국반도체학술대회, 강원도 하이원리조트, Feb. 13-15, 2023
고속 락킹 속도를 가지는 완전 디지털 PLL
; 한결, 김종선 ; 2022 제5회 반도체공학회 종합학술대회, 서울 aT 센터, pp. 90, Dec. 7, 2022
고성능 디지털 PLL 주파수 증배기의 설계
; 한결, 김종선 ; 2022 한국전자파학회 하계종합학술대회, 라마다프라자 제주호텔, 제주도, pp. 573, Aug 17-20, 2022 고성능 디지털 지터감쇠기의 설계
; 김승준, 김종선 ; 2022 한국전기전자학회 하계학술대회, 제주대학교 아라컨벤션홀, 제주도, pp. 1, Aug. 11-13, 2022
빠른 lock time을 가지는 완전 디지털 PLL
; 진정훈, 김종선 ; 2022 반도체공학회 하계학술대회, 부산 아난티 힐튼, pp. 95, July 11-13,? 2022
빠른 power-on 특성 다중-위상 디지털 주파수 증배기
; 김승준, 김종선 ; 2022 반도체공학회 하계학술대회, 부산 아난티 힐튼, pp. 93, July 11-13, 2022? 가변 해상도 TDC를 이용한 분수배 주파수 합성기
; 장채영, 김종선 ; 2022 반도체공학회 하계학술대회, 부산 아난티 힐튼, pp. 94, July 11-13, 2022 1.6-3.2 GHz TDC 기반 fast-lock 클럭 주파수 증배기
; 진정훈, 김승준, 김종선 (우수논문상 수상) ; 2021 제4회 반도체공학회 종합학술대회, 서울 드래곤시티호텔, Dec. 15, 2021? 고속 저전력 SerDes를 위한 224 Gbps 쿼드-레인 fast-lock PAM4 CDR
; 김승준, 김태연, 한결, 김종선 ; 2021 제4회 반도체공학회 종합학술대회, 서울 드래곤시티호텔, Dec. 15, 2021
6.4 GHz 디지털 클럭 주파수 증배기
; 최성욱, 진정훈, 김승준, 장채영, 김종선 ; 2021 한국전자파학회 하계종합학술대회, August 18-21, 2021
A 56Gb/s 디지털 PAM4 CDR
; 김태연, 김승준, 김종선 ; 2021 반도체공학회 하계학술대회, 남해 아난티 리조트, July 12-14, 2021
8.0 GHz fast-lock 차동 디지털 MDLL 주파수 증배기
; 최성욱, 김종선 (우수논문상 수상) ; 2020 제3회 반도체공학회 종합학술대회, 양재동 aT센터, Dec. 16, 2020
TDC 기반의 DCC 내장형 고속 Digital DLL ; 김태연, 김종선 ; 2020 제3회 반도체공학회 종합학술대회, 양재동 aT센터, Dec. 16, 2020
25 Gbps 저전력 PI-기반 완전 디지털 CDR
; 황희재, 김태연, 최성욱, 김종선 ; 2020 대한전자공학회 하계학술대회, 제주도 , Aug. 19-21, 2020 8.0 GHz 고속 디지털 MDLL 주파수 증배기
; 최성욱, 김종선 (우수포스터논문상 수상) ; 2020 한국전기전자학회 하계학술대회, 한양대 , Aug. 13, 2020 100 Gbps 4-채널 SerDes 리시버
; 황희재, 김태연, 김종선 ; 2020 한국전기전자학회 하계학술대회, 한양대 , Aug. 13, 2020 듀티-사이클 보정 기능을 내장한 완전-디지털 고속 DLL ; 김태연, 김종선 ; 제27회 한국반도체 학술대회 (The 27th Korean Conference on Semiconductors), Feb. 12, 하이원리조트, 2020
25Gbps 저전력 디지털 CDR
; 황희재, 김종선 ; 2019 제2회 반도체공학회 학술대회, 양재동 aT센터, Dec. 18, 2019
듀티-사이클 보정회로 내장 지연라인을 사용하는 고속 디지털 DLL
; 김태연, 김종선 (우수포스터논문상 수상) ; 2019 제2회 반도체공학회 학술대회, 양재동 aT센터, Dec. 18, 2019
안티-디더링 로우-지터 MDLL 주파수 합성기
; 이창준, 김종선 ; 2019 제2회 반도체공학회 학술대회, 양재동 aT센터, Dec. 18, 2019
저전력 디지털 시리얼링크 리시버
; 황희재, 김종선 ; 2019 한국전기전자학회 하계학술대회, 고려대 자연계캠퍼스, Aug. 9, 2019 저전력 초고속 시리얼링크 수신기 ; 이종혁, 김종선 ; 2019 한국전기전자학회 하계학술대회, 고려대 자연계캠퍼스, Aug. 9, 2019 듀티-사이클 보정회로를 내장한 디지털 고정지연루프 회로 ; 김태연, 김종선 (우수논문상 수상) ; 2019 한국전기전자학회 하계학술대회, 고려대 자연계캠퍼스, Aug. 9, 2019 시리얼링크용 초고속 클럭 및 데이터 ?복구 회로 ; 박건후, 김종선 ; 2019 한국전기전자학회 하계학술대회, 고려대 자연계캠퍼스, Aug. 9, 2019 안티-바운드리 스위칭 고해상도 디지털 DLL ; 김태연, 김종선 ; 2019 SoC 학술대회, 한밭대학교 유성캠퍼스, May 17-18, 2019 저전력 21 Gb/s 시리얼링크 송수신기 ; 이종혁, 김종선 ; 2019 SoC 학술대회, 한밭대학교 유성캠퍼스, May 17-18, 2019 다중-위상 선택 주입을 이용한 Fractional-N 주파수합성기 ; 윤준섭, 이창준, 김종선 (Chip-Design Contest 우수논문상 수상)? ; 제26회 한국반도체 학술대회 (The 26th Korean Conference on Semiconductors), Feb., 웰리힐리파크, 2019 고속 Memory를 위한 유사-차동 하이브리드 듀티-사이클 보정기 ; 황희재, 김종선 ; 제26회 한국반도체 학술대회 (The 26th Korean Conference on Semiconductors), Feb., 웰리힐리파크, 2019 초고속 시리얼 링크를 위한 저전력 직병렬 변환기 ; 박건후, 김종선 ; 2018 SoC 학술대회, 성균관대학교, May, 2018 고속 DRAM용 0.8-3.2GHz 전전력 듀티-사이클 보정회로 ; 황희재, 김종선 (우수 포스터 논문상 수상) ; 2018 한국전기전자학회 학술대회, 2018 저전력 고속-락킹 디지털 듀티-사이클 보정기 ; 황희재, 김종선 (우수 포스터 논문상 수상) ; 2018 SoC 학술대회, May, 2018 Post-DDR4 SDRAM을 위한 빠른 락킹 특성의 고속 DLL 설계 ; by Dongjun Park and Jongsun Kim (Best 포스터 논문상 수상)? ; 제25회 한국반도체 학술대회 (The 25th Korean Conference on Semiconductors), Feb., 2018 다중-위상 선택주입을 이용한 완전 디지털 Fractional-N 주파수 합성기 ; by junsub Yun and Jongsun Kim (최우수논문상 수상)? ; 제25회 한국반도체 학술대회 (The 25th Korean Conference on Semiconductors), Feb., 2018 위상 선택 주입을 이용한 디지털 주파수 합성기 ; 윤준섭, 김종선 ; 2017 SoC 학술대회, May, 2017 온-칩 네트워크를 위한 저전력 직병렬 변환기 ; 윤준섭, 김종선 ; 2017 SoC 학술대회, May, 2017 고속 Memory를 위한 완전 디지털 지연고정루프 ; 박동준, 김종선 ; 2017 SoC 학술대회, May, 2017 빠른 락킹 타임을 가지는 MDLL 클럭 주파수 증배기 ; 박동준, 김종선 ; 2017 SoC 학술대회, May, 2017 AMOLED 디스플레이를 위한 고효율 삼중 모드 부스트 변환기 ; 이승형, 김종선 ; 2017 SoC 학술대회, May, 2017 모바일 DRAM용 저전력 고주파수 듀티 보정회로 ; 황희재, 김종선 ; 2017 SoC 학술대회, May, 2017 A 10 Gbps CDR for Wireless Chip-to-Chip Communication ; by junsub Yun, Dongjun Park, and Jongsun Kim ; 제24회 한국반도체 학술대회 (The 24th Korean Conference on Semiconductors), 2017 A Multi-Phase Fractional-Ratio Frequency Multiplier ; by junsub Yun, Dongjun Park, and Jongsun Kim ; 제24회 한국반도체 학술대회 (The 24th Korean Conference on Semiconductors), 2017 고속 DRAM용 혼성 모드 DCC ; by junsub Yun and Jongsun Kim ; 2016 한국전기전자학회 학술대회, July 5, 2016 SDRAM용 고속 디지털 지연고정루프 ; by junsub Yun and Jongsun Kim ; 2016 한국전기전자학회 학술대회, July 5, 2016 DDR4 SDRAM을 위한 3중 검색 알고리즘을 이용하는 안티-하모닉 디지털 지연고정루프 ; by junsub Yun and Jongsun Kim ; 2016 SoC 학술대회, May, 2016 자동 이득 제어 회로를 이용한 와이드 다이나믹 레인지 RMS전력 검출기 ; by D. Lee and Jongsun Kim ; 2014 SoC 학술대회, 2014 Design of MDLL-based low-power high-performance clock generators ; Jongsun Kim ; 2014 대한전자공학회 하계학술대회, 2014 고성능 CMOS 하이브리드 듀티 사이클 보정 회로의 설계 ; by S. Han and Jongsun Kim ; 2012 SoC 학술대회, April, 2012 (우수상 수상) |
