|
International journal papers Selected Journal Papers 2024
-A shared TDC-based fast-lock all-digital DLL using a DCC-embedded delay line ; by Taeyeon Kim and Jongsun Kim
; Microelectronics Journal, Vol 149, pp. 1-7, 2024, Article No. 106251 (Elsevier, England, SCIE, Print ISSN: 0026-2692, Online ISSN: 1879-2391) ; DOI: https://doi-org.libproxy.hongik.ac.kr/10.1016/j.mejo.2024.106251 -A fast-lock variable-gain TDC-based N/M-ratio MDLL clock multiplier ; by Chaeyoung Jang and Jongsun Kim
; Electronics, Vol. 12, No. 19, pp. 1-13, Oct. 4, 2023 (SCIE, ISSN: 2079-9292) ; DOI: https://doi.org/10.3390/electronics12194136 -A fast-lock all-digital clock generator for energy efficient chiplet-based systems ; by Junghoon Jin, Seungjun Kim, and Jongsun Kim
; IEEE Access, Vol. 10, pp. 124217-124226, Nov. 14, 2022 (SCIE, ISSN: 2169-3536) ; DOI: 10.1109/ACCESS.2022.3224451 -A cost-effective and compact all-digital dual-loop jitter attenuator for built-off-test applications ; by Seungjun Kim, Junghoon Jin, and Jongsun Kim
; Electronics, Vol. 11, No. 21, pp. 1-12, Nov. 7, 2022 (SCIE, ISSN: 2079-9292) ; DOI: https://doi.org/10.3390/electronics11213630 -An N/M-ratio all-digital clock generator with a Pseudo-NMOS comparator-based programmable divider ; by Jongsun Kim
; Electronics, Vol. 11, No. 2, pp. 1-12, Jan. 14, 2022 (SCIE, ISSN: 2079-9292) ; DOI: https://doi.org/10.3390/electronics11020261 -A Fast lock all-digital MDLL using a cyclic Vernier TDC for burst-mode links ; by Dongjun Park, Sungwook Choi, and Jongsun Kim
; Electronics, Vol. 10, No. 2, pp. 1-9, Jan. 15, 2021 (SCIE, ISSN: 2079-9292) ; DOI: https://doi.org/10.3390/electronics10020177 -A low-jitter 2.4 GHz all-digital MDLL with a dithering jitter reduction scheme for 256 times frequency multiplication ; by Dongjun Park and Jongsun Kim ; IEICE Electronics Express, Vo.. 17, No. 19, pp. 1-5, Sep. 23, 2020 (SCIE, ISSN : 1349-2543) ; DOI: https://doi.org/10.1587/elex.17.20200296
-A 100 Gb/s Quad-lane SerDes Receiver with a PI-based Quarter-Rate All-Digital CDR ; by Heejae Hwang and Jongsun Kim ; Electronics, Vol. 9, No. 7, pp. 1-16, July 9, 2020 (SCIE, ISSN: 2079-9292) ; DOI: https://doi.org/10.3390/electronics9071113 -A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-based All-Digital DLL ; by Dongjun Park and Jongsun Kim ; Circuits, Systems, and Signal Processing (CSSP), Vol. 39, No. 4, pp. 1715-1734, April 20, 2020 (SCIE, print ISSN 0278-081X) (online: Aug. 8, pp. 1-20, 2019, Electronic ISSN 1531-5878) ; DOI: https://doi.org/10.1007/s00034-019-01230-x -A wide-range all-digital phase inversion DLL for high-speed DRAMs ; by Jongsun Kim ; Analog Integrated Circuits and Signal Processing (AICSP), Vol. 102, No. 1, Jan. pp. 39-51, 2020 (online: Sep. 5, 2019) (SCI, ISSN 0925-1030) ; DOI: https://doi.org/10.1007/s10470-019-01535-6 -A 0.8-3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links ; by Heejae Hwang and Jongsun Kim ; IEICE Electronics Express, Sep. 17, Vol. 16. No. 19, pp. 1-5, Oct. 10, 2019 (SCIE) ; DOI: https://doi.org/10.1587/elex.16.20190505
-A low-power 3.52 Gbps SerDes with a MDLL frequency multiplier for high-speed on-chip networks ; by Jongsun Kim and Hyungsik Shin ; Journal of Semiconductor Technology and Science (JSTS), Vol. 18, No. 6, Dec., 2018 (SCIE) ; DOI: www.jsts.org/html/journal/journal_files/.../Year2018Volume18_06_02.pdf -An anti-boundary switching fine-resolution digital delay-locked loop ; by Jongsun Kim ; Analog Integrated Circuits and Signal Processing (AICSP), Vol. 96, No. 3, pp 445-454, Sep., 2018 (SCI) ; DOI: https://doi.org/10.1007/s10470-018-1206-5 -A low-power fast-lock DCC with a digital duty-cycle adjuster for LPDDR3 and LPDDR4 DRAMs ; by Jongsun Kim and SW Han ; IEICE Electronics Express, Vol. 17, No. 7, pp. 1-9, Apr. 22, 2018 (SCIE) ; ; DOI: https://doi.org/10.1587/elex.15.20180156 -A fast-locking all-digital multiplying DLL for fractional-ratio dynamic frequency scaling ; by Jongsun Kim and SW Han ; IEEE Transactions on Circuits and Systems II (TCAS-II), Vol. 65, No. 3, pp. 276-280, March, 2018 (SCI) ; DOI: 10.1109/TCSII.2017.2688369 -An ahti-harmonic MDLL for phase aligned on-chip clock multiplication ; by Jongsun Kim and B-H Bae ; IEICE Electronics Express, Vol. 15, No. 5, pp. 1-11, Feb. 15, 2018 (SCIE) ; DOI: https://doi.org/10.1587/elex.15.20180042 -A high-speed SerDes transceiver for wireless proximity communication ; by Jongsun Kim and Jintae Kim ; Journal of Semiconductor Technology and Science (JSTS), Vol. 18, No. 1, pp. 42-48, Feb., 2018 (SCIE) ;DOI:http://www.jsts.org/html/journal/journal_files/2018/02/Year2018Volume18_01_07.pdf -An all-digital delay-locked loop using a lock-in pre-search algorithm ; by Jongsun Kim ; Journal of Semiconductor Technology and Science (JSTS), Vol. 17, No. 6, pp. 825-831, Dec., 2017 (SCIE) ; DOI: http://www.jsts.org/html/journal/journal_files/2017/12/Year2017Volume17_06_11.pdf -A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs ; by Junsub Yoon, Seoweon Heo, and Jongsun Kim ; IEICE Electronics Express, Vol. 14, No. 2, Jan. 25, 2017 (SCIE) ; DOI: https://doi.org/10.1587/elex.13.20161020 -A 2-4 GHz Fast-locking Frequency Multiplying Delay-Locked Loop ; by Jongsun Kim and B. Bae ; IEICE Electronics Express, Vol. 14, No. 2, Jan. 25, 2017 (SCIE) ; DOI: https://doi.org/10.1587/elex.13.20161056 -A High-Resolution Dual-Loop Digital DLL ; by Jongsun Kim and S. Han ; Journal of Semiconductor Technology and Science (JSTS), Vol. 16, No. 4, pp., Aug., 2016 (SCIE) ; DOI: http://www.jsts.org/html/journal/journal_files/2016/08/Year2016Volume16_04_16.pdf -An Area-efficient Multi-Phase Fractional-Ratio Clock Frequency Multiplier ; by S. Han, Jongtae Lim, and Jongsun Kim ; Journal of Semiconductor Technology and Science (JSTS), Vol. 16, No. 1, Feb. pp.143-146, 2016 (SCIE) ; DOI: http://www.jsts.org/html/journal/journal_files/2016/02/Year2016Volume16_01_15.pdf -5 GHz All-Digital Delay-locked Loop for Future Memory Systems Beyond double data rate 4 synchronous dynamic random access memory ; by D. Lee and Jongsun Kim ; IET Electronics Letters (EL), Vol. 51, Issue 24, pp. 1973-1975, Nov. 19, 2015 (SCI) ; DOI: 10.1049/el.2015.2876 ; https://ieeexplore.ieee.org/document/7335666 -A Single Chip Li-Ion Battery Protection IC with Low Standby Mode Auto Release ; by Seunghyeong Lee, Yongjae Jeong, Yungwi Song, and Jongsun Kim ; Journal of Semiconductor Technology and Science (JSTS), Vol. 15, No. 4, pp. 445-453, Aug. 2015 (SCIE) ; DOI: http://www.jsts.org/html/journal/journal_files/2015/08/Year2015Volume15_04_02.pdf -Programmable Fractional-Ratio Frequency Multiplying Clock Generator ; by S. Han, Jintae Kim, and Jongsun Kim ; IET Electronics Letters (EL), Vol. 50, Issue 3, pp. 163-165, Jan. 2014 (SCI) ; DOI: 10.1049/el.2013.2857 ; https://ieeexplore.ieee.org/document/6731739 -A Reset-Free Anti-Harmonic Programmable MDLL Based Frequency Multiplier ; by Geontae Park, Hyungtak Kim and Jongsun Kim ; Journal of Semiconductor Technology and Science (JSTS), Vol. 13, No. 5, pp. 459-464, Oct. 2013 (SCIE) ; DOI: http://www.jsts.org/html/journal/journal_files/2013/10/Year2013Volume13_05_06.pdf -A 0.5-2.0 GHz Dual-Loop SAR-Controlled Dyty-Cycle Corrector Using a Mixed Search Algorithm ; by S. Han and Jongsun Kim ; Journal of Semiconductor Technology and Science (JSTS), Vol. 13, No. 2, pp. 152-156, April, 2013 (SCIE) ; DOI: http://www.jsts.org/html/journal/journal_files/2013/04/Year2013Volume13_02_08.pdf? -An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling ; by G. Byun, Y. Kim, Jongsun Kim, S. Tam, and M. Frank Chang ; IEEE Journal of Solid-State Circuits (JSSC), Vol. 47, Jan. 2012 (SCI) ; DOI: 10.1109/JSSC.2011.2164709 -Hybrid Duty-Cycle Corrector Circuit with Dual Feedback Loop ; by S. Han and Jongsun Kim ; IET Electronics Letters (EL), Vol. 47, Issue 24, pp. 1311-1313, Nov., 2011 (SCI) ; DOI: 10.1049/el.2011.2710 ; https://ieeexplore.ieee.org/document/6088036 -A low-overhead and low-power RF Transceiver for short-distance on- and off-chip interconnects ; by Jongsun Kim, G. Byun, and M. Frank Chang ; IEICE Transactions on Electronics, Vol. E94.C, No. 5, pp. 854-857, May, 2011 (SCIE) ; DOI: https://doi.org/10.1587/transele.E94.C.854 - A Low-power Wideband Multi-Frequency Synthesizer for Mobile TV Tuner ICs ; by H. Ju and Jongsun Kim ; IEICE Electronics Express, Vol. 7, No. 2, pp. 92-97, Jan., 2010 (SCIE) ; DOI: https://doi.org/10.1587/elex.7.92 -Area-efficient Digitally Controlled CMOS Feedback Delay Element with Programmable Duty Cycle ; by Jongsun Kim ; IEICE Electronics Express, Vol. 6, No. 4, pp. 193-197, Feb., 2009 (SCIE) ; DOI: https://doi.org/10.1587/elex.6.193 ? -A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems ; by Jongsun Kim, B.C. Lai, M. F. Chang, Ingrid Verbauwhede ; IEEE Transactions on Computers (TC), Vol. 57, No. 12, pp. 1714-1720, December, 2008 (SCI) ; DOI: 10.1109/TC.2008.96 -Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication ; by Jongsun Kim, Ingrid Verbauwhede, M. Frank Chang ; IEEE Transactions on VLSI Systems (TVLSI), pp. 881-894, Vol. 15, No. 8, August, 2007 (SCI) ; DOI: 10.1109/TVLSI.2007.900739
-A 5.6-mW 1-Gb/s/pair Pulsed Signaling Transceiver for a Fully AC Coupled Bus ; by Jongsun Kim, Ingrid Verbauwhede, M. Frank Chang ; IEEE Journal of Solid-State Circuits (JSSC), Vol 40, Issue 6, pp. 1331-1340, 2005 (SCI) ; DOI: 10.1109/JSSC.2005.848030 -Advanced RF/Baseband Interconnect Schemes for Intra- and Inter-ULSI Communications ; by M. Frank Chang, Ingrid Verbauwhede, Charles Chien, Zhiwei Xu, Jongsun Kim, Jenwei Ko, Qun Gu, and Bo-Cheng Lai ; IEEE Transactions on Electron Devices (T-ED), Vol 52, No. 7, pp. 1271-1285, 2005. (SCI) ; DOI: 10.1109/TED.2005.850699 -A 2.5V, 72-Mbit 2.0Gbyte/s Packet-Based DRAM with a 1.0Gbps/pin Interface ; by C. Kim, K.-H. Kyung, W.-P. Jeong, J.-S. Kim, B.-S. Moon, J.-W. Chai, S.-M. Yim and S.-I. Cho ; IEEE Journal of Solid-State Circuit (JSSC), Vol.34, No.5, pp.645-652, May, 1999 (SCI) Domestic journal papers -PVT 변화 보상 기능을 가지는 시간-디지털 변환기 (A Time-to-Digital Converter with PVT Compensation Capability) ; by 신은호, 김종선 ; 전기전자학회논문지, Vol. 27, No. 3, pp 3234-3238, Sep., 2023 (ISSN: 1226-7244) -고속-락킹 디지털 주파수 증배기 ; by 이창준, 김종선 ; 전기전자학회논문지, Vol. 22, No. 4, pp 1158-1622, Dec., 2018 (ISSN: 1226-7244) -안티-바운드리 스위칭 디지털 지연고정루프 ; by Junsub Yoon and Jongsun Kim ; 전기전자학회논문지, Dec., 2017 -High Efficiency Triple Mode Boost DC-DC Converter Using Pulse-Width Modulation ; by Seunghyeong Lee, S. Han, and Jongsun Kim ; Journal of the IEIE, Vol. 52, No.2, pp. 265-272, Feb. 2015 -A CMOS RF Power Detector using an AGC Loop ; by Dongyeol Lee and Jongsun Kim ; Journal of the IEIE, Nov. 2014 -A 13-Gbps low-swing low-power near-ground signaling transceiver ; by Jahyun Ku, Bongho Bae, and Jongsun Kim ; Journal of the IEIE, Apr. 2014? -Design of clock duty-cycle correction circuits for high-speed SoCs ; by S. Han and Jongsun Kim ; Journal of KIISR, Vol. 18, No. 5, pp. 51-58, Oct., 2013 -A CMOS duty cycle corrector using dynamic frequency scaling for coarse and fine tuning adjustment ; by S. Han and Jongsun Kim ; Journal of the IEEK, 2012 -Design of an Integrated High Voltage Pulse Generation Circuit for Driving Piezoelectric Printer Heads ; by Kyoungrok Lee and Jongsun Kim ; Journal of KIIEE, Vol. 25, No. 2, pp. 1-8, Feb., 2011 -A Simple Phase Interpolator based Spread Spectrum Clock Generator Technique ; by Kyoungrok Lee, J. You, and Jongsun Kim ; Journal of the IEEK, Vol. 47, SD, pp. 7-13, Oct., 2010 |
